The invention relates to a circuit arrangement comprising an integrated semiconductor circuit, which circuit comprises a casing with a plurality of connection leads, stray capacitances with equal temperature coefficients existing between a first connection lead and the two adjacent, second and third, connection leads.
In an integrated semiconductor circuit, which is generally accommodated in a so-called "dual in-line" housing, stray capacitances arise between adjacent connection leads.
However, in many cases it is desirable to minimize the capacitance value or the temperature dependence of said stray capacitance between the connection leads of such an integrated semiconductor circuit. This is of particular importance for high-impedance signal processing circuits, resonant circuits, oscillators etc.
It may be possible to compensate for the temperature coefficient of the undesired stray capacitance by connecting an external capacitance having an opposite temperature coefficient to the integrated semiconductor circuit. However, as a result of this the overall capacitance increases and in many cases the field of application of the semiconductor circuit is restricted to an undesired extent.
It is known from GB-PS No. 12 41 285 to neutralize the undesired base-collector capacitance of a transistor in a transistor amplifier by means of an additional capacitance which is integrated in the semiconductor body of the transistor. However, it is not possible to compensate in this way for the stray capacitances between the connection leads of an integrated semiconductor circuit.